32172 Datasheet, PDF (477/875 Pages) Renesas Technology Corp – 32-bit RISC Single-chip Microcomputers

12
SERIAL I/O
12.1 Outline of Serial I/O
TXD0
RXD0
TXD1
RXD1
SIO0
SIO0 Transmit Buffer Register
SIO0 Transmit Shift Register
SIO0 Receive Shift Register
Transmit/
Receive
Control Circuit
Transmit interrupt
Receive interrupt
Transmit DMA transfer request
Receive DMA transfer request
SIO0 Receive Buffer Register
UART
mode
CSIO
mode
When external clock is selected
BCLK
BCLK,
BCLK/8,
BCLK/32,
BCLK/256
Clock
Divider
1/16
1
(Set value + 1)
Baud Rate
Generator
(BRG)
When internal clock is selected
1/2
CSIO mode
When internal clock is selected
When UART mode is selected
SIO1
SIO1 Transmit Shift Register
SIO1 Receive Shift Register
Transmit/
Receive
Control Circuit
Transmit interrupt
Receive interrupt
Transmit DMA transfer request
Receive DMA transfer request
TXD2
RXD2
SIO2
SIO2 Transmit Shift Register
SIO2 Receive Shift Register
Transmit/
Receive
Control Circuit
Transmit interrupt
Receive interrupt
Transmit DMA transfer request
Receive DMA transfer request
TXD3
RXD3
SIO3
SIO3 Transmit Shift Register
SIO3 Receive Shift Register
Transmit/
Receive
Control Circuit
Transmit interrupt
Receive interrupt
Transmit DMA transfer request
Receive DMA transfer request
Note 1: When BCLK is selected, the BRG set value is subject to limitations.
Note 2: SIO2 and SIO3 do not have the SCLKI/SCLKO functions.
Figure 12.1.1 Block Diagram of SIO0-SIO3
To Interrupt
Controller
To DMA3
To DMA4
SCLKI0/ SCLKO0
To Interrup
Controller
To DMA6
To DMA3
SCLKI1/ SCLKO1
To DMA0, 7
To DMA5
To Interrup
Controller
To DMA4, 9
To DMA8
12-6
Rev.1.0