7905 Datasheet, PDF (470/565 Pages) List of Unclassifed Manufacturers – LINEAR INTEGRATED CIRCUITS 3-TERMINAL VOLATGE REGULATORS

APPENDIX
Appendix 2. Control registers
D-A control register (Address 9616)
b7 b6 b5 b4 b3 b2 b1 b0
Bit
Bit name
0 D-A0 output enable bit
1 D-A1 output enable bit
Function
0: Output is disabled.
1: Output is enabled. (Notes 1, 2)
0: Output is disabled.
1: Output is enabled. (Notes 1, 2)
At reset R/W Reference
0
RW 13-3
0
RW
7 to 2 Nothing is assigned.
Undefined —
Notes 1: Pin DAi is multiplexed with an analog input pin or serial input/output pin. When a D-Ai output enable bit = “1” (in other words,
output is enabled.), however, the corresponding pin cannot function as any other multiplexed input/output pin (including a
programmable I/O port pin).
2: When not using the D-A converter, be sure to clear this bit to “0.”
b7
b0
D-A register i (i = 0 and 1) (Addresses 9816 and 9916)
Bit
Function
7 to 0 Any value in the range from 0016 through FF16 can be set (Note), and this
value will be D-A converted and will be output.
Note: When not using the D-A converter, be sure to clear the contents of these bits to “0016.”
At reset R/W
0 RW
Reference
13-3
Flash memory control register (Address 9E16)
b7 b6 b5 b4 b3 b2 b1 b0
Bit
Bit name
Function
At reset R/W Reference
0 RY/BY status bit
0 : BUSY (Automatic programming or erase operation 1
is active.)
1 : READY (Automatic programming or erase operation
has been completed.)
RO ^19-10
19-11
1 CPU reprogramming mode select bit 0 : Flash memory CPU reprogramming mode is invalid. ⁰
RW
1 : Flash memory CPU reprogramming mode is valid.
(Notes 1, 2)
2 The value is “0” at reading.
0
—
3 Flash memory reset bit (Note 3) Writing “1” into this bit discontinues the access to the 0
RW
internal flash memory. This causes the built-in flash
(Note 4)
memory circuit being reset.
4 The value is “0” at reading.
0
—
5 User ROM area select bit
0 : Access to boot ROM area
(Valid in boot mode) (Note 5) 1 : Access to user ROM area
7, 6 The value is “0” at reading.
0
RW
(Note 2)
0
—
Notes 1: In order to set this bit to “1,” write “0” followed with “1” successively; while in order to clear this bit “0,” write “0.”
2: Writing to this bit must be performed in an area other than the internal flash memory.
3: This bit is valid when the CPU reprogramming mode select bit (bit 1) = “1”: on the other hand, when the CPU
reprogramming mode select bit = “0,” be sure to fix this bit to “0.” Rewriting of this bit must be performed with the CPU
reprogramming mode select bit = “1.”
4: After writing of “1” to this bit, be sure to confirm the RY/BY status bit (bit 0) becomes “1”; and then, write “0” to this bit.
5: When MD1 = Vss level, this bit is invalid. (It may be either “0” or “1.”)
7905 Group User’s Manual Rev.1.0
20-39