H838076R Datasheet, PDF (445/669 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Super Low Power Series

Section 16 Serial Communication Interface 4 (SCI4)
During reception, the SCI4 operates as shown below.
1. The SCI4 initialization is performed in synchronization with the synchronous clock input or
output and starts reception.
2. The SCI4 stores received data from the LSB to MSB of SR4.
3. After reception, the SCI4 checks that RDRF = 0 and whether receive data is ready for being
transferred from SR4 to RDR4.
4. When confirms that an overrun error has not occurred, the RDRF bit is set to 1 and the
received data is stored in RDR4. At this time, when the RIE bit in SCR4 is set to 1, an RXI is
generated. When an overrun error is detected by checking, the ORER flag is set to 1. The
RDRF bit retains the previously set value. If the RIE bit in SCR4 is set to 1, an ERI is
generated.
5. An overrun error is detected when the next data reception is completed with the RDRF bit in
SCSR4 set to 1. The received data is not transferred from SR4 to RDR4.
Note: Reception cannot be performed when the error flag is set to 1. Before reception, confirm
that the ORER and RDRF flags are cleared to 0.
Figure 16.7 shows an operation example of reception.
Synchronous clock
Serial data
RDRF
ORER
LSI operation
User operation
Bit 7
Bit 0
Bit 7
1 frame
Bit 0
Bit 1
Bit 6
1 frame
Bit 7
RXI
RDRF
generated cleared
RXI
generated
Data read
from RDR4
RDR4 has not
been read from
(RDRF = 1)
Figure 16.7 Receive Operation Example
ERI generated
by overrun error
Overrun error
processing
Rev. 4.00 Aug 23, 2006 Page 373 of 594
REJ09B0093-0400