HD404889_03 Datasheet, PDF(43/197 Page) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip LCD Circuit

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HD404889_03 Datasheet, PDF (43/197 Pages) Renesas Technology Corp – Low-Voltage AS Microcomputers with On-Chip LCD Circuit

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HD404889/HD404899/HD404878/HD404868 Series

Interrupts

There are a total of nine interrupt sources, comprising wakeup input (WU0 to WU3), external interrupts

(INT0, INT1), timer/counter (timer A, timer B, timer C, timer D) interrupts, a serial interface interrupt, and

an A/D converter interrupt.

Each interrupt source is provided with an interrupt request flag, interrupt mask, and vector address, used for

storing and controlling interrupt requests. In addition, an interrupt enable flag is provided to control

interrupts as a whole.

Of the interrupt sources, timers B and D share the same vector address, and the A/D converter and serial

interface also share the same vector address. Software must therefore determine which of the interrupt

sources is requesting an interrupt at the start of interrupt handling.

Interrupt control bits and interrupt handling:

The interrupt control bits are mapped onto RAM addresses $000 to $003 and $022 to $023, and can be

accessed by RAM bit manipulation instructions. However, the interrupt request flags (IF) cannot be set by

software. When the MCU is reset, the interrupt enable flag (IE) and interrupt request flags (IF) are

initialized to 0, and the interrupt masks (IM) are initialized to 1.

Figure 9 shows a block diagram of the interrupt control circuit, table 2 shows interrupt priorities and vector

addresses, and table 3 lists the conditions for executing interrupt handling for each of the nine kinds of

interrupt source. When the interrupt request flag is set to 1 and the interrupt mask is cleared to 0, an

interrupt is requested. If the interrupt enable flag is set to 1 at this time, interrupt handling is started. The

vector address corresponding to the interrupt source is generated by the priority control circuit.

The interrupt handling sequence is shown in figure 10, and the interrupt handling flowchart in figure 11.

When an interrupt is accepted, execution of the previous instruction is completed in the first cycle. In the

second cycle, the interrupt enable flag (IE) is reset. In the second and third cycles, the contents of the carry

flag, status flag, and program counter are saved on the stack. In the third cycle, a jump is made to the

vector address and instruction execution is resumed from that address.

In each vector address area, a JMPL instruction should be written that branches to the start address of the

interrupt routine. In the interrupt routine, the interrupt request flag that caused interrupt handling must be

reset by software.

Table 2 Vector Addresses and Interrupt Priorities

Interrupt Source

RESET

WU0 to WU3

INT

Timer A

Timer B, D

Timer C

Serial interface, A/D converter

Priority

Vector Address

$0000

$0002

$0004

$0006

$0008

$000A

$000C

$000E

Rev.6.00, Sep.08.2003, page 43 of 197

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