H83062 Datasheet, PDF (413/1021 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 11 Watchdog Timer
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3062 chip
internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to
initialize external system devices. Note that there is no RESO pin in the versions with on-chip
flash memory.
Bit 7
WRST
0
1
Description
[Clearing conditions]
• Reset signal at RES pin.
• Read WRST when WRST =1, then write 0 in WRST.
(Initial value)
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of
the reset signal generated if TCNT overflows during watchdog timer operation. Note that there is
no RESO pin in the versions with on-chip flash memory.
Bit 6
RSTOE Description
0
Reset signal is not output externally
1
Reset signal is output externally
(Initial value)
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.
11.2.4 Notes on Register Rewriting
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte instructions. Figure 11.2 shows the format of data written to
TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be
contained in the lower byte of the written word. The upper byte must contain H'5A (password for
TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT
or TCSR.
Rev. 6.00 Mar 18, 2005 page 365 of 970
REJ09B0215-0600