S3A7 Datasheet, PDF (4/133 Pages) Renesas Technology Corp – 32-bit ARM Cortex-M4 microcontroller

S3A7
1. Overview
Table 1.3
System (2/2)
Feature
Watchdog Timer (WDT)
Independent Watchdog Timer (IWDT)
Functional description
The Watchdog Timer (WDT) is a 14-bit down-counter. It can be used to reset this MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The
refresh-permitted period can be set to refresh the counter and used as the condition to detect
when the system runs out of control. See section 26, Watchdog Timer (WDT) in User's Manual.
The independent watchdog timer (IWDT) consists of a 14-bit down-counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset
this MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the
timer operates using an independent, dedicated clock source, it is particularly useful in
returning this MCU to a known state as a fail safe mechanism when the system runs out of
control. The watchdog timer can be triggered automatically on reset, underflow, or refresh
error, or by a refresh of the count value in the registers. See section 27, Independent
Watchdog Timer (IWDT) in User's Manual.
Table 1.4
Interrupt control
Feature
Interrupt Controller Unit (ICU)
Functional description
The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC
module and DMAC module. The ICU also controls NMI interrupts. See section 14, Interrupt
Controller Unit (ICU) in User's Manual.
Table 1.5
Event link
Feature
Event Link Controller (ELC)
Functional description
The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral
modules as event signals to connect them to different modules, enabling direct interaction
between the modules without CPU intervention. See section 19, Event Link Controller (ELC) in
User's Manual.
Table 1.6
Direct memory access
Feature
Data Transfer Controller (DTC)
DMA Controller (DMAC)
Functional description
This MCU incorporates a Data Transfer Controller (DTC) that performs data transfers when
activated by an interrupt request. See section 18, Data Transfer Controller (DTC) in User's
Manual.
This MCU incorporates an 4-channel DMA Controller (DMAC) module that can transfer data
without the CPU. When a DMA transfer request is generated, the DMAC transfers data stored
at the transfer source address to the transfer destination address. See section 17, DMA
Controller (DMAC) in User's Manual.
Table 1.7
Feature
External bus
External bus interface
Functional description
 CS area: Connected to the external devices (external memory interface)
 QSPI area: Connected to the QSPI (external device interface)
R01DS0263EU0100 Rev.1.00
Feb 23, 2016
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