RJK0330DPB-01_15 Datasheet, PDF (4/7 Pages) Renesas Technology Corp – Silicon N Channel Power MOS FET Power Switching

RJK0330DPB-01
Static Drain to Source on State Resistance
vs. Temperature
10
Pulse Test
8
6
I_D = 5 A, 10 A, 20 A
4
V_GS = 4.5 V
2
10 V
5 A, 10 A, 20 A
0
–25 0 25 50 75 100 125 150
Case Temperature Tc (°C)
Dynamic Input Characteristics
50
I_D = 45 A
40
30
V_DS
V_DD = 25 V
10 V
20
V_GS
16
12
20
8
10
V_DD = 25 V
4
10 V
0
0
0
20 40 60 80 100
Gate Charge Qg (nc)
Maximum Avalanche Energy vs.
Channel Temperature Derating
100
I_AP = 22 A
80
V_DD = 15 V
duty < 0.1 %
Rg ≥ 50 Ω
60
40
20
0
25 50 75 100 125 150
Channel Temperature Tch (°C)
Preliminary
10000
Typical Capacitance vs.
Drain to Source Voltage
3000
Ciss
1000
300
100
Coss
Crss
30 _{VGS = 0}
f = 1 MHz
10
0
10
20
30
Drain to Source Voltage V_DS (V)
Reverse Drain Current vs.
Source to Drain Voltage
50
10 V
40
5V
Pulse Test
30
20
10
V_GS = 0, –5 V
0
0.4 0.8 1.2 1.6 2.0
Source to Drain Voltage V_SD (V)
R07DS0266EJ0500 Rev.5.00
Mar 01, 2011
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