R32C120_10 Datasheet, PDF (4/103 Pages) Renesas Technology Corp – RENESAS MCU

R32C/120 Group
1. Overview
1.1.2 Performance Overview
Table 1.1 and Table 1.2 show the performance overview of the R32C/120 Group.
Table 1.1 R32C/120 Group Performance (1/2)
Unit
Function
Performance
CPU
Central processing R32C/100 Series CPU Core
unit
• Basic instructions: 108
• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)
• Multiplier: 32-bit × 32-bit  64-bit
• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit  64-bit
• IEEE-754 floating point standard: Single precision
• 32-bit barrel shifter
• Operating mode: Single-chip mode
Memory
Flash memory: 128/256 Kbytes
RAM: 12/20 Kbytes
Data flash: 4 Kbytes × 2 blocks
E²dataFlash: none ⁽¹⁾/4 Kbytes
Refer to Table 1.3 for details
Voltage
Detector
Low voltage
detector
Optional ⁽²⁾
Low voltage detection interrupt
Clock
Clock generator
• 4 circuits (main clock, sub clock, PLL, on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/re-oscillation
detection
• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable
• Low power modes: Wait mode, stop mode
Interrupts
Interrupt vectors: 261
External interrupt inputs: NMI, INT × 6, key input × 4
Interrupt priority levels: 7 levels
Watchdog Timer
15 bits × 1 (selectable input frequency from prescaler output)
Automatic timer start function is available
DMA
DMAC
4 channels
• Cycle-steal transfer mode
• Request sources: 44
• 2 transfer modes: Single transfer, repeat transfer
DMAC II
• Can be activated by any peripheral interrupt source
• 3 transfer functions: Immediate data transfer, calculation transfer,
chained transfer
I/O Ports
Programmable
I/O ports
• 2 input-only ports
• 84 CMOS inputs/outputs
• A pull-up resistor is selectable for every 4 input ports
Notes:
1. Please contact a Renesas sales office to use the non-E²dataFlash version.
2. Please contact a Renesas sales office to use the optional feature.
REJ03B0236-0110 Rev.1.10 Mar 02, 2010
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