HD74HC112 Datasheet, PDF (4/7 Pages) Hitachi Semiconductor – Dual J-K Flip-Flops (with Preset and Clear)

HD74HC112
Switching Characteristics (C_L = 50 pF, Input t_r = t_f = 6 ns)
Item
Pulse width
Setup time
Hold time
Removal time
Output rise/fall
time
Input capacitance
Symbol VCC (V)
tw
2.0
4.5
6.0
tsu
2.0
4.5
6.0
th
2.0
4.5
6.0
trem
2.0
4.5
6.0
tTLH, tTHL 2.0
4.5
6.0
Cin
—
Ta = 25°C
Ta = –40 to +85°C
Min Typ Max Min Max Unit
Test Conditions
80 — — 100
— ns Clear, Clock
16 9 —
20
—
14 — —
17
—
100 — — 125
— ns J or K to Clock
20 3 —
25
—
17 — —
21
—
5 ——
5
— ns Clock to J or K
5 –2 —
5
—
5 ——
5
—
100 — — 125
— ns Clear to Clock
20 2 —
25
—
17 — —
21
—
— — 75
—
95 ns
— 5 15
—
19
— — 13
—
16
— 5 10
—
10 pF
Test Circuit
VCC
VCC
Input
Pulse generator
Zout = 50 Ω
Input
Pulse generator
Zout = 50 Ω
Preset
Q
Clock
J
K
Q
Clear
Output
Output
C_L = 50 pF
C_L = 50 pF
Note: C_L includes the probe and jig capacitance.
Rev.2.00, Oct 11, 2005 page 4 of 6