HD151TS303RP Datasheet, PDF (4/9 Pages) Renesas Technology Corp – Spread Spectrum Clock for EMI Solution

HD151TS303RP
AC Electrical Characteristics / Clock Output & SSC Clock Output
Ta = 25°C, VDD = 3.3 V, C_L = 30 pF
Item
Symbol Min
Cycle to cycle jitter ^{*1, 2}
t_CCS
—
Typ
| 250 |
Max
| 300 |
Unit
Test Conditions
ps SSCCLKOUT,
Fig1, 24 MHz
Notes
SSCOFF
SEL1:0 = 10
—
| 250 | | 300 |
SSCCLKOUT,
Fig1, 24 MHz
SSC= ±0.25%
SEL1:0 = 11
—
| 250 | | 300 |
SSCCLKOUT,
Fig1, 24 MHz
SSC= ±1.5%
SEL1:0 = 01
—
| 250 | | 300 |
CLKOUT,
Output frequency ^{*1, 2}
Fig1, 24 MHz & 48 MHz
23.8
—
24.2 MHz SSCCLKOUT,
SSCOFF
XIN = 48 MHz
SEL1:0 = 10
23.7
—
24.3
SSCCLKOUT,
XIN = 48 MHz
SSC= ±0.25%
SEL1:0 = 11
23.4
—
24.6
SSCCLKOUT,
XIN = 48 MHz
SSC= ±1.5%
SEL1:0 = 01
23.8
—
24.2
CLKOUT,
24 MHz
47.3
—
48.7
CLKOUT,
Slew rate^*1
Clock duty cycle ^*1
Output impedance ^*1
48 MHz
t_SL
1.0
—
—
V/ns @48 MHz CLKOUT 0.4 V to 2.4 V
45
50
55
%
—
30
—
Ω
Spread spectrum
modulation frequency ^*1
—
33
—
KHz SSCCLKOUT =
24 MHz
XIN = 48 MHz
Input clock frequency
Stabilization time ^*1,3
10
—
60
MHz
—
—
2
ms
Notes: 1. Parameters are target of design. Not 100% tested in production.
2. Cycle to cycle jitter and output frequency are included spread spectrum modulation.
3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after
power up.
SSCCLKOUT
(or CLKOUT)
tcycle n
tcycle n+1
t _CCS = (tcycle n) - (tcycle n+1)
Figure 1 Cycle to cycle jitter
Rev.6.00 Apr 07, 2006 page 4 of 8