2SJ687_15 Datasheet, PDF (4/10 Pages) Renesas Technology Corp – SWITCHING P-CHANNEL POWER MOS FET

2SJ687
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
<R>
<R>
Zero Gate Voltage Drain Current
IDSS
Gate Leakage Current
IGSS
Gate to Source Cut-off Voltage
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
RDS(on)3
Input Capacitance
Ciss
VDS = −20 V, VGS = 0 V
VGS = m12 V, VDS = 0 V
VDS = −10 V, ID = −1 mA
VDS = −10 V, ID = −10 A
VGS = −4.5 V, ID = −10 A
VGS = −3.0 V, ID = −10 A
VGS = −2.5 V, ID = −10 A
VDS = −10 V,
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage ^Note
Reverse Recovery Time
Reverse Recovery Charge
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
VGS = 0 V,
f = 1 MHz
VDD = −10 V, ID = −10 A,
VGS = −4.5 V,
RG = 3 Ω
VDD = −16 V,
VGS = −4.5 V,
ID = −20 A
IF = −20 A, VGS = 0 V
IF = −20 A, VGS = 0 V,
di/dt = −100 A/μs
Note Pulsed
MIN.
−0.6
20
TYP.
−1.2
5.4
7.1
10.8
4400
1070
760
36
220
270
310
57
12
28
0.85
200
240
MAX.
−10
m100
−1.45
7.0
9.0
20
1.5
UNIT
μA
nA
V
S
mΩ
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = −12 → 0 V
−
IAS ^BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS(−)
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS(−)
VGS
Wave Form
0 ^10%
VDS(−)
90%
VDS
VDS
Wave Form ⁰
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = −2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet D18719EJ2V0DS