M32C8B Datasheet, PDF (394/406 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
M32C/8B Group
25. Usage Notes
25.11 Serial Interfaces
25.11.1 Changing UiBRG Register (i = 0 to 4)
Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register. When bits CLK1 and CLK0 are
changed, set the UiBRG register again.
25.11.2 Clock Synchronous Mode
25.11.2.1 Selecting External Clock
If an external clock is selected, meet the following conditions while the external clock is held “H” when the
CKPOL bit in the UiC0 register (i = 0 to 4) is set to 0 (transmit data output at the falling edge and receive data
input at the rising edge of the serial clock), or while the external clock is held “L” when the CKPOL bit is set to
1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock)
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled).
• Set the RE bit in the UiC1 register to 1 (receive operation enabled).
• The TI bit in the UiC1 register is 0 (data in the UiTB register).
The RE bit setting is not required for a transmit-only operation.
25.11.2.2 Receive Operation
• In clock synchronous mode, the serial clock is controlled by the transmit control circuit. Set the UARTi-
associated registers for a transmit operation as well, even if the MCU is used only for receive operation.
Dummy data is output from the TXDi pin while receiving if the TXDi pin is set to output mode.
• If data is received continuously, an overrun error occurs when the RI bit in the UiC1 register is 1 (data in the
UiRB register) and the seventh bit of the next data is received in the UARTi receive shift register. And the
OER bit in the UiRB register becomes 1 (overrun error). In this case, a read from the UiRB register returns
undefined values. If an overrun error occurs,the IR bit in the SiRIC register is not changed to 1.
• The following two conditions must be satisfied to use continuous receive mode (UiRRM bit is set to 1).
(1) The CKDIR bit in the UiMR register is set to 1 (external clock).
(2) The RTS function is not used.
To receive data continuously under the other conditions, set the UiRRM bit to 0 (continuous receive mode
disabled), and write dummy data to the UiTB register every time a receive operation is completed.
25.11.3 UART Mode
Set the UiERE bit in the UiC1 register after setting the UiMR register.
25.11.4 Special Mode 1 (I²C Mode)
To generate the start condition, stop condition, or restart condition, set the STSPSEL bit in the USMR4 register
to 0. Then, wait for a half clock cycle of the serial clock or more to change individual condition generation bit
(the STAREQ bit, STPREQ bit, or RSTAREQ bit) from 0 to 1.
(Technical update: TN-16C-130A/EA)
REJ09B0450-0050 Rev.0.50 Oct 31, 2008
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