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HA16107P Datasheet, PDF (38/40 Pages) Hitachi Semiconductor – PWM Switching Regulator for High-performance Voltage Mode Control
HA16107P/FP, HA16108P/FP
This gate resistance RG is given by the following equation.
RG = (VG/IG) – (VG × tON)/Qg, RG = RG1 + RG2
IG : Gate input peak current
VG : Gate drive voltage wave high value (equal to power supply voltage of IC)
tON : Power MOS FET turn-on time
tOFF : Power MOS FET turn-off time
Qg : Gate charge according to Figure 9
VDS
VDS
VGS
(V)
(V)
VGS
Qg (nc)
Figure 9 Power MOS FET Dynamic Input Characteristics
Refer to the power MOS FET catalog for information on tON and Qg.
By dividing RG into RG1 and RG2, it is possible for speed to be slowed when the power MOS FET is on, and
increased when off.
Power MOS FET on and off times when mounted, tON’ and tOFF’, are as follows.
tON’ = tON + Qg(RG1 + RG2)/VG
tOFF’ = tOFF + Qg ⋅ RG2/VG
<Actual Example>
When driving a power MOS FET and 2SK1567 with an HA16107, etc.
(RG1 = 100 Ω, RG2 = 20 Ω, VG = 15 V)
tON’ = 70 ns + 36 nc ⋅ (100 Ω + 20 Ω)/(15 V) = 360 (ns)
tOFF’ = 135 ns + 36 nc ⋅ (20 Ω)/(15 V) = 183 (ns)
Generally, the gate resistance values in the case of this circuit configuration are on the order of 100 to 470 Ω for RG1
and 10 to 47 Ω for RG2.
Rev.4.00 Jun 15, 2005 page 38 of 39