HA16107P Datasheet, PDF (11/40 Pages) Hitachi Semiconductor – PWM Switching Regulator for High-performance Voltage Mode Control

HA16107P/FP, HA16108P/FP
Timer Latch and ON/OFF Timer
The HA16107 has a built-in timer-latch function. The HA16108 has a built-in ON/OFF timer function.
The timer-latch function is an overvoltage protection function that combines latched shutdown of PWM output with a
timer function to vary the time until latched shutdown occurs according to the overcurrent value. A dedicated voltage
detection pin is provided in addition to Vref overvoltage protection.
The ON/OFF timer function is equivalent to the above timer-latch function without the latch. If overcurrent is detected
continuously, PWM output shuts down temporarily, then normal operation resumes. This process repeats, temporary
shutdown alternating with normal operation.
Both the timer-latch function in the HA16107 and the ON/OFF function in the HA16108 wait for an interval after
overcurrent detection before shutting down PWM output. The interval is determined by capacitor C_TM and the value of
the charge/discharge current supplied internally from the IC. Normal operation therefore continues if a single
overcurrent spike is detected, while if continuous overcurrent is detected, the current and voltage droop curves for the
secondary-side output have sharp characteristics.
1. Use of Timer-Latch Pin (HA16107)
 Timer-Latch Usage
See external circuit 1 in the following diagram. Under continuous overcurrent, the CML switch turns on,
charging C_TM with 12 µA. PWM output shuts down when the voltage at pin 15 exceeds 7 V.
 Overvoltage Protection Usage
See external circuit 2 in the diagram. This configuration is suitable when overvoltage is detected by an OVP
signal received through an optocoupler from the DC output on the secondary side of an AC/DC converter.
PWM output shuts down when the OVP signal allows the voltage at the TL pin to exceed 7 V. The shutdown is
latched. V_IN must go below approximately 6.5 V (V_INR2) to release the latched state.
• External circuit 1
15
C_TM
16 µA
from CML
OVP with
latch timer
4 µA
HA16107
7.0 V ^VTH
• External circuit 2
V_IN
OVP signal
(from secondary)
T_L
Latch
(PWM output shuts down)
V_TL
B
A
0V
t
OCL detected continuously
(activating pulse-by-pulse current limiter)
Notes: 1. Path A is followed if the OCL input stops before V_TH is reached.
2. Path B is followed if OCL is detected continuously until the latch point is reached.
3. The latch function is cleared when V_IN goes below approximately 7.0 V.
Rev.4.00 Jun 15, 2005 page 11 of 39