M66291GP_15 Datasheet, PDF (35/128 Pages) Renesas Technology Corp – ASSP (USB2.0 Device Controller)

M66291GP/HP
(12) CTSQ (Control Transfer Stage) Bits (b2~b0)
These bits indicate the present stage in the control transfer. Refer to Figure 2.7.
000 : Idle or Setup Stage
001 : Control Read Transfer Data Stage
010 : Control Read Transfer Status Stage
011 : Control Write Transfer Data Stage
100 : Control Write Transfer Status Stage
101 : Control Write No Data Transfer Status Stage
110 : Control Transfer Sequence Error (refer to below)
111 : Reserved
The control transfer sequence error is described below. When this error occurs, the EP0_PID bits are set to
“1x” (stall state).
<At control read transfer>
• OUT token is received when data is never transferred against the IN token of the data stage.
• IN token is received at status stage.
• Data packet other than the zero-length packet is received at status stage.
<At control write transfer>
• IN token is received when ACK response is never made against the OUT token of the data
stage.
• OUT token is received in status stage.
<At control write no data transfer>
• OUT token is received in status stage.
<Others>
• Data exceeding in size set by the EP0 Packet Size Register is received (the EPB_EMP_OVR
bit of the Interrupt Status Register 3 is set to “1”).
In case the amount of received data exceeds the wLength value in the request at the data stage of the
control write transfer, it is not recognized as the control transfer sequence error.
Setup token receive
Setup token receive
Setup token receive
[CTSQ bits ="1xx"]
Control transfer
sequence error
(Note )
(5)
Error detection
[CTSQ bits ="000"]
Setup stage
ACK transmit
(1)
[CTSQ bits ="001"]
Control read
transfer
data stage
OUT token
receive
(2)
[CTSQ bits ="010"]
Control read
transfer
status stage
ACK transmit
(4)
[CTSQ bits ="000"]
Idle stage
ACK
transmit
(1)
[CTSQ bits ="011"]
Control write
transfer
data stage
IN token receive
(3)
[CTSQ bits ="100"]
Control write
transfer
status stage
ACK
receive
ACK transmit
: CTRTinterrupt has occurred
(1) Setup stage completion
[CTSQ bits ="101"]
Control write
ACK
receive
transfer no data
(1)
status stage
(2) Control read transfer
status stage transition
(3) Control write transfer
status stage transition
(4) Control transfer completion
(5) Control transfer
sequence error
Note : When the SERR bit is set to "1" and the control transfer sequence error causes the CTRT interrupt to
occur, the CTSQ bit values (1xx) are retained until "0" is written to the CTRT bit (interrupt is cleared).
Further, even after the completion of the next set up stage, the CTRT interrupt due to the completion
of the set up stage is not occurred until "0" is written to the CTRT bit.
When the SERR bit is set to "0", if setup token is received, the CTSQ bits changes to "000".
Figure 2.7 Control Transfer Transition
Rev1.01 2004.11.01 page 33 of 122