M66291GP_15 Datasheet, PDF (17/128 Pages) Renesas Technology Corp – ASSP (USB2.0 Device Controller)

M66291GP/HP
2.3 Sequence Bit Clear Register
Q Sequence Bit Clear Register (SEQUENCE_BIT)
<Address : H’04>
b15 14 13 12 11 10
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
b
15~7
6~0
Bit name
Reserved. Set it to “0”.
SQCLR
Sequence Bit Clear
9
8
7
6
5
4
3
2
1 b0
SQCLR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
<H/W reset : H'0000>
<S/W reset : H'0000>
<USB bus reset : ->
Function
RW
Q Write
00
0{
0 : Invalid (Ignored when written)
1 : Clear Sequence bit
b6 corresponds to EP6, ---b1 corresponds to EP1 and b0
corresponds to EP0.
(1) SQCLR (Sequence Bit Clear) Bits (b6~b0)
These bits clear the sequence bit (the bit controlled by H/W) and turns the data PID into DATA 0 PID.
This bit immediately returns to “0” after writing “1”.
In the transfers after the sequence bit is cleared, the sequence bit is toggled through H/W control.
At S/W reset (USBE bit = “1”) and USB bus reset, the sequence bit of each endpoint is not cleared.
Note : Be sure to set the response PID of the endpoint whose sequence bit is desired to be cleared to NAK (EP0_PID
bits = “00”/EPi_PID bits = “00”) before writing “1” to this bit.
Rev1.01 2004.11.01 page 15 of 122