M30201_M Datasheet, PDF (340/415 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY

Power Control
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.11.2 Stop Mode Set-Up
Settings and operation for entering stop mode are described here.
Operation (1) Enables the interrupt used for returning from stop mode.
(2) Sets the interrupt enable flag (I flag) to “1”.
(3) Clearing the protection and setting every-clock stop bit to “1” stops oscillation and causes the
processor to go into stop mode.
(1) Setting interrupt to cancel stop mode
Interrupt control register
KUPIC
ADIC
SiTIC(i=0, 1)
SiRIC(i=0, 1)
TAiIC(i=0)
TXiIC(i=0 to 2)
TBiIC(i=0, 1)
[Address 004D16]
[Address 004E16]
[Address 005116, 005316]
[Address 005216, 005416]
[Address 005516]
[Address 005616 to 005816]
[Address 005A16, 005B16]
b7
b0
b7
0
Interrupt priority level select bit
Make sure that the interrupt priority
level of the interrupt which is used to
cancel the wait mode is higher than
the processor interrupt priority(IPL) of
the routine where the WAIT
instruction is executed.
(2) Interrupt enable flag (I flag) “1”
INTiIC(i=0, 1)
b0
[Address 005D16, 005E16]
Interrupt priority level select bit
Make sure that the interrupt priority level of the
interrupt which is used to cancel the wait mode is
higher than the processor interrupt priority(IPL) of
the routine where the WAIT instruction is executed.
Reserved bit
Must be set to “0”
(3) Canceling protect
b7
b0
1
Protect register [Address 000A16]
PRCR
Enables writing to system clock control registers 0 and 1
(addresses 000616 and 000716)
1 : Write-enabled
(3) Setting operation clock after returning from stop mode
(When operating with XIN after returning)
(When operating with XCIN after returning)
b7
0
0
b0 System clock control register
b7
[Address 000616] CM0
1
1
b0 _{System clock control register 0}
[Address 000616] CM0
Main clock (XIN-XOUT) stop bit
On
System clock select bit
XIN, XOUT
As this register becomes setting mentioned above when
operating with XIN (count source of BCLK is XIN),
the user does not need to set it again.
Port XC select bit
XCIN-XCOUT generation
System clock select bit
XCIN, XCOUT
WsA(cesohsWA(lecuteeshochnlneitutetshcbonnsirtiptsoetboesugtripooretriasecugtttoer_“^{rieias1ncrotte}_”g_“^{ei.fb1nrowTBe}_”^{g.fbhciCtwTBeoehLhcimCtbKXoehLeom}IN^{ibKXstsh,eoIsNiXsstsbeh,eC}_istXsttt^I_bse^NieCpnit)ttct^Iogs,^{Niapnrt)ctmnhog,aXnertetmnhocnuXnetetssocibnuoeetetssnlribeoeeesdecnlrdeoetesdtecbadeoatsibttetbaontastibovthotonetet}“_tovho1nwseet”“^{ea1hnbewsm”eeedahnbefemeotedoonrtfeiepotmsooertesieepmrseta.eestiettrtetiia.nnatittgtggiinnaawsgggiyniatwss.hiyntietXs.hmtCeXImN}c^Cl^Io^Ncclokck
(3) All clocks off (stop mode)
b7
b0
0 0 0 01
System clock control register [Address 000716]
CM1
All clock stop control bit
1 : All clocks off (stop mode)
Reserved bit
Must be set to “0”
All clocks off (stop mode)
Figure 2.11.5. Example of stop mode set-up
327