M65818AFP Datasheet, PDF (34/39 Pages) Renesas Technology Corp – Digital Amplifier Processor of S-Master Technology

M65818AFP
• ∆ΣBlock: AC dithering Rch Phase (bit21: ACDRPOL).
"L"…Same phase "H"…Reverse phase
• ∆Σ Block: AC dithering Selection (bit22,bit23,bit24: ACDSEL0,ACDSEL1,ACDSEL2).
Refer to Table 6-3-3.
7.1. AC Characteristics Lists.
AC Characteristics
Parameter
XfsoIN duty ratio
XfsiIN duty ratio
SCSHIFT pulse time
SCDT setup time
SCDT hold time
SCLATCH pulse width
SCLATCH setup time
SCLATCH hold time
BCK pulse width
DATA setup time
DATA hold time
LRCK setup time
LRCK hold time
EXBCK pulse time
EXWCK setup time
EXWCK hold time
EXDATA L / R setup time
EXDATA L / R hold time
EXDATA L / R output delay time
EXWCK output delay time
DSD128fs pulse width
DSD64fs pulse width
DSD64fs setup time
DSD64fs hold time
DSD L / R setup time
DSD L / R hold time
SYNC pulse width
Symbol
duty(XfsoIN)
duty(XfsiIN)
tw(SCSHIFT)
tsu(SCDT)
th(SCDT)
tw(SCLATCH)
tsu(SCLATCH)
th(SCLATCH)
tw(BCK)
tsu(DATA)
th(DATA)
tsu(LRCK)
th(LRCK)
tw(EXBCK)
tsu(EXWCK)
th(EXWCK)
tsu(EXDATA)
th(EXDATA)
tpd(EXDATA)
tpd(EXWCK)
tw(DSDCK128)
tw(DSDCK64)
tsu(DSDCK64)
th(DSDCK64)
tsu(DATA)
th(DATA)
tw(SYNC)
(Ta=25 °C, PWM Vdd=5V, DVdd=3.3V)
Conditions
512fsi
256fsi
Output load capacity 10 [pF]
Output load capacity 10 [pF]
mode 1, 3
mode 1, 3
mode 1, 2, 3, and 4
mode 1, 2, 3, and 4
Min.
40
30
40
160
80
80
160
160
160
35
20
20
20
20
35
20
20
20
20
70
140
40
40
40
40
160
Typ.
50
50
50
1.0
1.0
Max.
60
70
60
Units
%
%
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
Rev.1.00, Sep.04.2003, page 34 of 38