M65818AFP Datasheet, PDF (31/39 Pages) Renesas Technology Corp – Digital Amplifier Processor of S-Master Technology

M65818AFP
*NOTE2; Selection of PWM output form
Pay attention in selection and setting above-mentioned that a noise may occur by internal clock changes when setting of
MCKSEL pin is changed and the serial control System2 mode:
bit17 (NSOBIT) and bit16 (NSSPEED).
Since especially MCKSEL pin sets up an internal master clock, use with a fixed value recommended.
In changing MCKSEL, initialization with INIT pin and a re-setup of all the bits by serial control are needed after
changing MCKCEL.
• Reverse Phase of PWM Output OUTL1(-) / OUTR1(-) (bit24:PWMHP)
"L"…PWM Output OUTL1(-) / OUTR1(-) are reverse phase as the PWM output OUTL1(+) / OUTR1(+) .
"H"…PWM Output OUTL1(-) / OUTR1(-) are same phase as the PWM output OUTL1(+) / OUTR1(+) .
In this mode, the signal which added OUTL1(-) / OUTR1(-) and OUTL2(-) / R2(-) by external resistance can be
given to LPF / Headphone Amplifier.
6.3. System2 Mode (Secondary side)
bit Flag Name Functional Explanation
H
L
INIT
1 MODE1
Mode Setting 1
"H" fixed

2 MODE2
Mode Setting 2
"L" fixed

3 IMCKSEL
Input Master Clock Selection 512fsi
256fsi
L
4 DSDFCO0
Filter Coefficient of Down
Refer to Table 6-3-1.
L
5 DSDFCO1
Sampling
L
6 SYNC
Resynchronization
L->H :
L
Resynchronization.
7 XFsoOEN
XfsoOUT pin output "enable" disable
enable
L
8 ASYNCEN2 Asynchronous Detection Flag for enable
disable
L
secondary Side
9 CHSEL
L / R inversion of PWM
Active
Non-active
L
output
10 DRPOL
∆ΣBlock: Rch Input Phase
Negative-phase
Positive-phase
L
11 SRCRST
Sampling Rate Converter
Active
Non-active
L
Reset
12
don't care

13 GIMUTE
Zero Mute at Gain Control
Active
Non-active
L
Input Clock
14 NSPMUTE
Duty 50 percent Mute of
PWM Output
Active
Non-active
L
15 PGMUTE
G_MUTE of PWM Output
Active
Non-active
L
Data
16 NSSPEED
∆Σ Block: Operation Speed 32fso
16fso
L
17 NSOBIT
∆Σ Block: Setting of Output 5 bits (31 value)
6 bits (63 value)
L
Bit Number
18 DCDRPOL
∆Σ Block: Rch Phase of DC
dithering
Negative-phase
Positive-phase
L
19 DCDSEL0
∆ΣBlock: DC dithering
Refer to Table 6-3-2
L
20 DSDSEL1
Selection
L
21 ACDRPOL
∆Σ Block: Rch Phase of AC Negative-phase
Positive-phase
L
dithering
22 ACDSEL0
∆Σ Block: AC dithering
Refer to Table 6-3-3
L
23 ACDSEL1
selection
L
24 ACDSEL2
L
Rev.1.00, Sep.04.2003, page 31 of 38