DF70854AD80FPV Datasheet, PDF (333/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

SH7080 Group
Section 9 Bus State Controller (BSC)
9.4.5 Refresh Timer Control/Status Register (RTCSR)
RTCSR specifies various items about refresh for SDRAM.
When writing to RTCSR, write data with setting the upper 16 bits to H'A55A to cancel write
protection.
Phase matching of the clock input to the refresh timer counter (RTCNT) is only performed on
power-on reset. Accordingly, if the timer is started with CKS[2:0] set to other than B'000, there
will be an error contained in the period until the first setting of the compare match flag.
Bit: 31
-
Initial value: 0
R/W: R/W
30
-
0
R/W
29
-
0
R/W
28
-
0
R/W
27
-
0
R/W
26
-
0
R/W
25
-
0
R/W
24
-
0
R/W
23
-
0
R/W
22
-
0
R/W
21
-
0
R/W
20
-
0
R/W
19
-
0
R/W
18
-
0
R/W
17
-
0
R/W
16
-
0
R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
CMF CMIE
CKS[2:0]
RRC[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to ⎯
16
All 0
R/W Write Protect Cancellation
When writing to RTCSR, write H'A55A to these bits to
cancel write protection. These bits are always read as 0.
15 to 8 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
CMF
0
R/W Compare Match Flag
This is a status flag which indicates that a compare match
occurs between the refresh timer counter (RTCNT) and
refresh time constant register (RTCOR). This bit is set or
cleared in the following conditions.
0: Clearing condition: When 0 is written in CMF after
reading out RTCSR during CMF = 1.
1: Setting condition: When the condition RTCNT =
RTCOR is satisfied.
R01UH0198EJ0500 Rev. 5.00
Mar 18, 2011
Page 275 of 1560