DF70854AD80FPV Datasheet, PDF (1004/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
SH7080 Group
18.7 Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states
described below.
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-
up resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 18.23 shows the timing of the bit synchronous circuit and table 18.6 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
Monitor SCL pin level
Monitor SCL pin level
SCL monitor
timing reference
clock
SCL
V_IH
Internal SCL
Figure 18.23 The Timing of the Bit Synchronous Circuit
Table 18.6 Time for Monitoring SCL
CKS3
CKS2
NF2CYC
Time for Monitoring SCL*¹
0
0
0
6.5
t *2
pcyc
1
5.5
t *2
pcyc
1
0
18.5
t *2
pcyc
1
17.5
t *2
pcyc
1
0
0
16.5
t *2
pcyc
1
15.5
t *2
pcyc
1
0
40.5
t *2
pcyc
1
39.5
t *2
pcyc
Notes: 1. SCL pin level is monitored after "time for monitoring SCL" has elapsed from the rising
edge of the reference clock for monitoring SCL.
2. t_pcyc indicates the period of the peripheral clock.
Page 946 of 1560
R01UH0198EJ0500 Rev. 5.00
Mar 18, 2011