H8S2628_10 Datasheet, PDF (318/658 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 8-Bit Timers
11.8.2 Conflict between TCNT Write and Increment
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the write
takes priority and the counter is not incremented. Figure 11.11 shows this operation.
φ
Address
TCNT write cycle by CPU
T₁
T₂
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 11.11 Conflict between TCNT Write and Increment
Rev. 4.00 Mar. 16, 2010 Page 270 of 606
REJ09B0155-0400