R1Q3A7236ABB_15 Datasheet, PDF (31/36 Pages) Renesas Technology Corp – 72-Mbit QDR™II SRAM 4-word Burst

Common
R1Q3A7236ABB / R1Q3A7218ABB Series
ID Register
-
#
Symbol
Revision
Type number
Start bit (0) ă Ň
number
(28 : 12)
Vendor JEDEC code
䊼
(31 :29)
(11 : 1)
䊼
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R 0 C M M M AWW 0 1 Q Q Q B O S 0 0 1 0 0 0 1 0 0 0 1 1 1
RRR
000
001
010
011
:
Q
Revison 0
0
II (QDR-II, DDR-II)
Revison 1
1 II+ (QDR-II+, DDR-II+)
Revison 2
Q
Revison 3
0 DDR
:
1 QDR
C
Q
0 36M&72M w/o ODT, 144M,288M 0 Latency=1.5 (@II), Latency=2.0 (@II+)
1 36M&72M w/ ODT
1
Latency=2.5 (@II+)
MMM
B
0 1 0 Density = 36Mb
0 Burst Length = 2 word burst
0 1 1 Density = 72Mb
1 Burst Length = 4 word burst
1 0 1 Density = 144Mb
O
1 1 0 Density = 288Mb
0 without ODT
A
1 with ODT
0 144M&288M w/o ODT, 36M,72M S
1 144M&288M w/ ODT
0 Common I/O
WW
1 Separate I/O
0 0 x9
1 0 x18
1 1 x36
TAP Controller State Diagram
1
Test Logic Reset
0
1
Run Test/Idle
0
1
Select DR Scan
0
1
Capture DR
0
0
Shift DR
1
1
Exit1 DR
0
0
Pause DR
1
0
Exit2 DR
1
Update DR
10
1
Select IR Scan
0
1
Capture IR
0
0
Shift IR
1
1
Exit1 IR
0
0
Pause IR
1
0
Exit2 IR
1
Update IR
10
Notes:
The value adjacent to each state transition in this figure represents the signal present at TMS at
the time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held
high for at least five rising edges of TCK.
Rev. 0.11 : 2013.01.15
R10DS0165EJ0011
PAGE:31