R1Q3A7236ABB_15 Datasheet, PDF (20/36 Pages) Renesas Technology Corp – 72-Mbit QDR™II SRAM 4-word Burst

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R1Q3A7236ABB / R1Q3A7218ABB Series
AC Characteristics (QDR-II, DDR-II series)
(Ta = 0 ~ +70°C @ R1Q*A*****BB-**R** series)
(Ta = -40 ~ +85°C @ R1Q*A*****BB-**I** series)
(V_DD = 1.8V ±0.1V, V_DDQ = 1.5V, V_REF = 0.75V)
-30
Parameter Symbol
Min Max
Clock
Average clock
cycle time
(K, /K, C, /C)
t_KHKH
3.00 8.40
Clock high time
(K, /K, C, /C)
t_KHKL
1.20
⎯
Clock low time
(K, /K, C, /C)
t_KLKH
1.20
⎯
-33
Min Max
3.30 8.40
1.32 ⎯
1.32 ⎯
-40
Min Max
4.00 8.40
1.60 ⎯
1.60 ⎯
-50
Min Max
5.00 8.40
2.00 ⎯
2.00 ⎯
⎯
⎯
Unit Notes
Min Max Min Max
⎯ ⎯ ⎯ ⎯ ns 8
⎯ ⎯ ⎯ ⎯ ns
⎯ ⎯ ⎯ ⎯ ns
Clock to /clock
(K to /K, C to /C)
t_KH/KH
1.35
⎯
1.49
⎯
1.80
⎯
2.20
⎯
⎯ ⎯ ⎯ ⎯ ns
/Clock to clock
(/K to K, /C to C)
t_/KHKH
1.35
⎯
1.49
⎯
1.80
⎯
2.20
⎯
⎯ ⎯ ⎯ ⎯ ns
Clock to
data clock
(K to C, /K to /C)
t_KHCH
0 1.35 0 1.49 0 1.80 0 2.20 ⎯ ⎯ ⎯ ⎯ ns
DLL/PLL Timing
Clock phase
jitter
t_KC var ⎯ 0.20 ⎯ 0.20 ⎯ 0.20 ⎯ 0.20 ⎯ ⎯ ⎯ ⎯ ns 3
(K, /K, C, /C)
Lock time
(K, C)
Cy-
t_KC lock 1024 ⎯ 1024 ⎯ 1024 ⎯ 1024 ⎯
⎯ ⎯⎯⎯
cle
2
K static to
DLL/PLL reset
t_KC reset
30
⎯
30
⎯
30
⎯
30
⎯
⎯ ⎯ ⎯ ⎯ ns
7
Output Times
C, /C high to
output valid
t_CHQV
⎯ 0.45 ⎯ 0.45 ⎯ 0.45 ⎯ 0.45 ⎯ ⎯ ⎯ ⎯ ns
9
C, /C high to
output hold
t_CHQX −0.45 ⎯ −0.45 ⎯ −0.45 ⎯ −0.45 ⎯
⎯ ⎯ ⎯ ⎯ ns
9
C, /C high to
echo clock t_CHCQV ⎯ 0.45 ⎯ 0.45 ⎯ 0.45 ⎯ 0.45 ⎯ ⎯ ⎯ ⎯ ns 9
valid
C, /C high to
echo clock hold
t_CHCQX
−0.45
⎯
−0.45
⎯
−0.45
⎯
−0.45
⎯
⎯ ⎯ ⎯ ⎯ ns
9
CQ, /CQ high
to
t_CQHQV ⎯ 0.25 ⎯ 0.27 ⎯ 0.30 ⎯ 0.35 ⎯ ⎯ ⎯ ⎯ ns 4, 7
output valid
CQ, /CQ high
to
output hold
t_CQHQX −0.25 ⎯ −0.27 ⎯ −0.30 ⎯ −0.35 ⎯
⎯ ⎯ ⎯ ⎯ ns 4, 7
C, /C high to
output high-Z
t_CHQZ
⎯ 0.45 ⎯ 0.45 ⎯ 0.45 ⎯ 0.45 ⎯ ⎯ ⎯ ⎯ ns 5, 6, 9
C, /C high to
output low-Z
t_CHQX1 −0.45 ⎯ −0.45 ⎯ −0.45 ⎯ −0.45 ⎯
⎯ ⎯ ⎯ ⎯ ns 5, 9
⎯
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯⎯⎯⎯ ⎯
Rev. 0.11 : 2013.01.15
R10DS0165EJ0011
PAGE:20