H8S2602 Datasheet, PDF (300/492 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Watchdog Timer
12.3 Operation
12.3.1 Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1.
When the WDT is used as a watchdog timer, and if TCNT overflows without being rewritten
because of a system malfunction or other error, an internal reset occurs and the internal chip states
can be reset.
TCNT does not overflow while the system is operating normally. Software must prevent TCNT
overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
In this case, select power-on reset by setting the RSTS bit of the RSTCSR to 0.
The internal reset signal is output for 518 states.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
The WDTOVF signal is output for 132 states when the RSTE bit = 1 of RSTCSR, and for 130
states when the RSTE bit = 0.
When the TCNT overflows in watchdog timer mode, the WOVF bit of the RSTCSR is set to 1.
If the RSTE bit of the RSTCSR has been set to 1, an internal reset signal for the entire LSI is
generated at TCNT overflow.
12.3.2 Interval Timer Mode
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows. Therefore, an interrupt can be generated at intervals.
When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested
at the time the OVF bit of the TCSR is set to 1.
Rev. 1.00 Jan. 21, 2008 Page 268 of 456
REJ09B0425-0100