H8S2602 Datasheet, PDF(29/492 Page) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

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H8S2602 Datasheet, PDF (29/492 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

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Section 10 16-Bit Timer Pulse Unit (TPU)

Table 10.1 TPU Functions ...................................................................................................... 156

Table 10.2 TPU Pins............................................................................................................... 159

Table 10.3 CCLR0 to CCLR2 (channels 0 and 3) .................................................................. 163

Table 10.4 CCLR0 to CCLR2 (channels 1, 2, 4, and 5) ......................................................... 163

Table 10.5 TPSC0 to TPSC2 (channel 0) ............................................................................... 164

Table 10.6 TPSC0 to TPSC2 (channel 1) ............................................................................... 164

Table 10.7 TPSC0 to TPSC2 (channel 2) ............................................................................... 165

Table 10.8 TPSC0 to TPSC2 (channel 3) ............................................................................... 165

Table 10.9 TPSC0 to TPSC2 (channel 4) ............................................................................... 166

Table 10.10 TPSC0 to TPSC2 (channel 5) ........................................................................... 166

Table 10.11 MD0 to MD3 .................................................................................................... 168

Table 10.12 TIORH_0 (channel 0) ....................................................................................... 170

Table 10.13 TIORL_0 (channel 0)........................................................................................ 171

Table 10.14 TIOR_1 (channel 1) .......................................................................................... 172

Table 10.15 TIOR_2 (channel 2) .......................................................................................... 173

Table 10.16 TIORH_3 (channel 3) ....................................................................................... 174

Table 10.17 TIORL_3 (channel 3)........................................................................................ 175

Table 10.18 TIOR_4 (channel 4) .......................................................................................... 176

Table 10.19 TIOR_5 (channel 5) .......................................................................................... 177

Table 10.20 TIORH_0 (channel 0) ....................................................................................... 178

Table 10.21 TIORL_0 (channel 0)........................................................................................ 179

Table 10.22 TIOR_1 (channel 1) .......................................................................................... 180

Table 10.23 TIOR_2 (channel 2) .......................................................................................... 181

Table 10.24 TIORH_3 (channel 3) ....................................................................................... 182

Table 10.25 TIORL_3 (channel 3)........................................................................................ 183

Table 10.26 TIOR_4 (channel 4) .......................................................................................... 184

Table 10.27 TIOR_5 (channel 5) .......................................................................................... 185

Table 10.28 Register Combinations in Buffer Operation ..................................................... 201

Table 10.29 Cascaded Combinations.................................................................................... 205

Table 10.30 PWM Output Registers and Output Pins .......................................................... 208

Table 10.31 Phase Counting Mode Clock Input Pins ........................................................... 212

Table 10.32 Up/Down-Count Conditions in Phase Counting Mode 1.................................. 214

Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2.................................. 215

Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 3.................................. 216

Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 4.................................. 217

Table 10.36 TPU Interrupts .................................................................................................. 220

Rev. 1.00 Jan. 21, 2008 Page xxix of xxxii

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