RJK0362DSP Datasheet, PDF (3/7 Pages) Renesas Technology Corp – Silicon N Channel Power MOS FET Power Switching

RJK0362DSP
Main Characteristics
Power vs. Temperature Derating
4.0
Test Condition :
When using the glass epoxy board
(FR4 40x40x1.6 mm), PW ≤ 10 s
3.0
2.0
1.0
0
50
100
150
200
Ambient Temperature Ta (°C)
Typical Output Characteristics
20
4.5 V
10 V
16
Pulse Test
3.2 V
12
3.0 V
8
2.8 V
4
V_GS = 2.6 V
0
2
4
6
8
10
Drain to Source Voltage V_DS (V)
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
160
Pulse Test
120
80
I_D = 10 A
40
5A
2A
0
4
8
12
16 20
Gate to Source Voltage V_GS (V)
REJ03G1653-0501 Rev.5.01 Apr 24, 2008
Page 3 of 6
Maximum Safe Operation Area
500
100
10 _µs
10
1
Opera^Dt^Cio^On^pi^en^{PraWtio=n11(Pm0Wsm}<^s
this area is
100
1^N₀^ot_s^e₎
µ_s
4
limited by R_DS(on)
0.1
Ta = 25°C
0.01 ^{1 shot Pulse}
0.1 0.3 1 3 10 30 100
Drain to Source Voltage V_DS (V)
Note 5 : When using the glass epoxy board
(FR4 40x40x1.6 mm)
Typical Transfer Characteristics
20
V_DS = 10 V
Pulse Test
16
12
8
4
25°C
Tc = 75°C
–25°C
0
1
2
3
4
5
Gate to Source Voltage V_GS (V)
Static Drain to Source on State Resistance
vs. Drain Current
100
Pulse Test
30
10 _{VGS = 5 V}
10 V
3
1
1 3 10 30 100 300 1000
Drain Current I_D (A)