RJK0353DSP Datasheet, PDF (3/7 Pages) Renesas Technology Corp – Silicon N Channel Power MOS FET Power Switching

RJK0353DSP
Main Characteristics
Power vs. Temperature Derating
4.0
Test Condition :
When using the glass epoxy board
(FR4 40x40x1.6 mm), PW ≤ 10 s
3.0
2.0
1.0
0
50
100
150
200
Ambient Temperature Ta (°C)
Typical Output Characteristics
50
4.5 V
10 V
3.2 V
40
Pulse Test
3.0 V
30
2.8 V
20
10
V_GS = 2.6 V
0
2
4
6
8
10
Drain to Source Voltage V_DS (V)
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
160
Pulse Test
120
80
40
I_D = 10 A
5A
2A
0
4
8
12
16 20
Gate to Source Voltage V_GS (V)
REJ03G1648-0401 Rev.4.01 Apr 24, 2008
Page 3 of 6
Maximum Safe Operation Area
500
10 µs
100
10
1
OthpiseararetDioaCnisOinperaPtiWon=(P11W0 ^mm_≤^ss110N0o^0s_te)^µ₅^s
limited by R_DS(on)
0.1
Ta = 25 °C
0.01 ^{1 shot Pulse}
0.1 0.3 1 3
10 30 100
Drain to Source Voltage V_DS (V)
Note 5 : When using the glass epoxy board
(FR4 40x40x1.6 mm)
Typical Transfer Characteristics
50
V_DS = 10 V
Pulse Test
40
30
20
10
Tc = 75°C
25°C
–25°C
0
1
2
3
4
5
Gate to Source Voltage V_GS (V)
Static Drain to Source on State Resistance
vs. Drain Current
100
Pulse Test
30
10
V_GS = 4.5 V
3
10 V
1
1 3 10 30 100 300 1000
Drain Current I_D (A)