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| PD44164182B_15 Datasheet, PDF (3/35 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM 2-WORD BURST OPERATION | |||
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μPD44164182B, μPD44164362B
Pin Arrangement
1
2
3
A CQ# VSS/72M A
B NC DQ9 NC
C NC
NC
NC
D NC
NC DQ10
E NC
NC DQ11
F NC DQ12 NC
G NC
NC DQ13
H DLL#
J NC
VREF
NC
VDDQ
NC
K NC
NC DQ14
L NC DQ15 NC
M NC
NC
NC
N NC
NC DQ16
P NC
NC DQ17
R TDO TCK
A
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD44164182B]
1M x 18
4
5
6
7
8
R, W# BW1# K# NC/144M LD#
A NC/288M K
BW0#
A
VSS
A
A0
A
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VSS
VSS
VSS
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VSS
VSS
VSS
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
A
A
A
VSS
A
A
C
A
A
A
A
C#
A
A
9
10
11
A VSS/36M CQ
NC
NC DQ8
NC DQ7 NC
NC
NC
NC
NC
NC DQ6
NC
NC DQ5
NC
NC
NC
VDDQ
VREF
ZQ
NC DQ4 NC
NC
NC DQ3
NC
NC DQ2
NC DQ1 NC
NC
NC
NC
NC
NC DQ0
A
TMS TDI
A0, A
DQ0 to DQ17
LD#
R, W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1.
2.
3.
ÃÃÃ# indicates active LOW.
Refer to Package Dimensions for the index mark.
2A, 7A, 10A and 5B are expansion addresses ç ç : 10A for 36Mb
: 10A and 2A for 72Mb
: 10A, 2A and 7A for 144Mb
: 10A, 2A, 7A and 5B for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0014EJ0200 Rev.2.00
October 6, 2011
Page 3 of 34
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