PD44164182B_15 Datasheet, PDF (11/35 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM 2-WORD BURST OPERATION

μPD44164182B, μPD44164362B
Bus Cycle State Diagram
LOAD NEW
ADDRESS
Count = 0
Load, Count = 2
Read
Load, Count = 2
Write
READ DOUBLE
Count = Count + 2
WRITE DOUBLE
Count = Count + 2
NOP,
Count = 2
Power UP
Supply voltage provided
NOP
NOP
NOP,
Count = 2
Load
Remarks 1. A0 is internally advanced in accordance with the burst order table.
Bus cycle is terminated after burst count = 2.
2. State machine control timing sequence is controlled by K.
R10DS0014EJ0200 Rev.2.00
October 6, 2011
Page 11 of 34