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| NP60N06PDK Datasheet, PDF (3/9 Pages) Renesas Technology Corp – N-channel Power MOS FET | |||
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NP60N06PDK
Electrical Characteristics (TA = 25°C)
Item
Symbol Min
Zero Gate Voltage Drain Current IDSS
Gate Leakage Current
IGSS
Gate to Source Threshold Voltage VGS(th)
1.5
Forward Transfer Admittance â1
| yfs |
30
Drain to Source On-state
Resistance â1
RDS(on)1
RDS(on)2
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Turn-on Delay Time
td(on)
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
Gate to Source Charge
QGS
Gate to Drain Charge
Body Diode Forward Voltage â1
QGD
VF(S-D)
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Note: *1. Pulsed test
Typ
2.1
54
6.4
7.0
2400
230
80
18
6
45
3
37
9
8
0.9
32
30
Max
1
±100
2.5
7.9
12.0
3600
350
150
40
20
90
10
56
1.5
Unit
μA
nA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
VDS = 60 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 μA
VDS = 5 V, ID = 30 A
VGS = 10 V, ID = 30 A
VGS = 4.5 V, ID = 15 A
VDS = 25 V,
VGS = 0 V,
f = 1 MHz
VDD = 30 V, ID = 30 A,
VGS = 10 V,
RG = 0 Ω
VDD = 48 V,
VGS = 10 V,
ID = 60 A
IF = 60 A, VGS = 0 V
IF = 60 A, VGS = 0 V,
di/dt = 100 A/μs
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
VGS = 20 â 0 V
50 Ω
VDD
BVDSS
ID IAS
VDD
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
PG.
RG
VGS
0
Ï
Ï = 1 μs
Duty Cycle ⤠1%
RL
VGS
VGS
Wave Form
10%
0
VDD
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
R07DS1296EJ0101 Rev.1.01
Dec 21, 2015
Page 3 of 7
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