M66280FP Datasheet, PDF (3/14 Pages) Mitsubishi Electric Semiconductor – 5120 x 8-BIT LINE MEMORY

M66280FP
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Output voltage
Power dissipation
Storage temperature
Symbol
VCC
VI
VO
Pd
Tstg
Ratings
−0.3 to +4.6
−0.3 to VCC + 0.3
−0.3 to VCC + 0.3
300
−55 to 150
(Ta = 0 to 70°C, unless otherwise noted)
Unit
Conditions
V
Value based on the GND pin
V
V
mW Ta = 25°C
°C
Recommended Operating Conditions
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
2.7
3.15
3.6
V
Supply voltage
GND

0

V
Operating temperature
Topr
0

70
°C
Electrical Characteristics
Item
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
High-level input current
Low-level input current
Off-state high-level output current
Off-state low-level output current
Average supply current during
operation
Input capacitance
Off-time output capacitance
(Ta = 0 to 70°C, V_CC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Symbol
Min
Typ Max Unit
Test Conditions
VIH
2.0

V
VIL

 0.8
V
VOH
VCC − 0.8 

V IOH = −4 mA
VOL

 0.55 V IOL = 4 mA
IIH

 1.0 µA VI = VCC WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 to D7
IIL

 −1.0 µA VI = GND WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 to D7
IOZH

 5.0
µA VO = VCC
IOZL

 −5.0 µA VO = GND
ICC

 70 mA VI = VCC, GND, Output open
tWCK, tRCK = 25 ns
CI

 10 pF f = 1 MHz
CO

 15 pF f = 1 MHz
Function
When write enable input WEB is set to "L", the contents of data inputs D0 to D7 are read in synchronization with a
rising edge of write clock input WCK to perform writing operation. When this is the case, the write address counter is
also incremented simultaneously.
When WEB is set to "H", the writing operation is inhibited and the write address counter stops.
When write reset input WRESB is set to "L", the write address counter is initialized.
When read enable input REB is set to "L", the contents of memory are output to data outputs Q0 to Q7 in
synchronization with a rising edge of read clock input RCK to perform reading operation. When this is the case, the
read address counter is incremented simultaneously.
When REB is set to "H", the reading operation is inhibited and the read address counter stops. The outputs are placed
in a high impedance state.
When read reset input RRESB is set to "L", the read address counter is initialized.
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
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