M5M5V5A36GP Datasheet, PDF (3/19 Pages) Renesas Technology Corp – 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM

BLOCK DIAGRAM
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
VDD
VDDQ
A0
19
A1
A2~18
ADDRESS
REGISTER
19
17
A1
D1
A0
D0
LINEAR/
INTERLEAVED
BURST
COUNTER
A1'
Q1
A0'
Q0
CLK
CKE#
ZZ
ADV
BWa#
BWb#
BWc#
BWd#
W#
G#
E1#
E2
E3#
19
WRITE ADDRESS
REGISTER
19
WRITE REGISTRY
AND
DATA COHERENCY
CONTROL LOGIC
READ
LOGIC
BYTE1
WRITE
DRIVERS
BYTE2
WRITE
DRIVERS
BYTE3
WRITE
DRIVERS
BYTE4
WRITE
DRIVERS
36
256Kx36
MEMORY
ARRAY
INPUT
REGISTER
VSS
DQa
DQPa
DQb
DQPb
DQc
DQPc
DQd
DQPd
Note3. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION
and timing diagrams for detailed information.
3/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0