M5M5V5A36GP Datasheet, PDF (1/19 Pages) Renesas Technology Corp – 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM

Preliminary
Notice: This is not final specification.
Some parametric limits are subject to change.
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
FEATURES
• Flow-Through Read mode, Single Late Write mode
• Fast access time: 7.5 ns and 8.5 ns
• Single 3.3V -5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V I/O
• Individual byte write (BWa# - BWd#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need
to control G#
• Snooze mode (ZZ) for power down
• Three chip enables for simple depth expansion
Package
100pin TQFP
FUNCTION
Synchronous circuitry allows for precise cycle control
triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs,
all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,
BWd#) and Read/Write (W#).
Write operations are controlled by the four Byte Write Enables
(BWa# - BWd#) and Read/Write(W#) inputs. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ).
The HIGH input of ZZ pin puts the SRAM in the power-down
state.
All read, write and deselect cycles are initiated by the ADV
LOW input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers.
PART NAME TABLE
Part Name
M5M5V5A36GP-75
M5M5V5A36GP-85
Access
7.5ns
8.5ns
Cycle
8.5ns
10ns
Active Current
(max.)
280mA
260mA
Standby Current
(max.)
30mA
30mA
1/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0