M32C86 Datasheet, PDF (289/505 Pages) Renesas Technology Corp – RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/86 Group (M32C/86, M32C/86T)
22. Intelligent I/O
Base Timer Control Register 11
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
G1BCR1
Address
012316
After Reset
X000 000X2
Bit
Symbol
Bit Name
Function
RW
Nothing is assigned. When write, set to "0".
(b0)
When read, its content is indeterminate.
0: The base timer is not reset by
RST1 ^{Base Timer Reset}
matching with the G1PO0 register
RW
Cause Select Bit 1 1: The base timer is reset by matching
with the G1PO0 register⁽¹⁾
0: The base timer is not reset by
RST2
Base Timer Reset
Cause Select Bit 2
applying "L" to the INT0 or INT1 pin
1: The base timer is reset by applying
RW
"L" to the INT0 or INT1 pin⁽²⁾
Reserved Bit
Set to "0"
RW
(b3)
Base Timer
0: Base timer is reset
BTS _{Start Bit}
1: Base timer starts counting
RW
UD0
UD1
b6b5
0 0 : Counter increment mode
RW
Counter Increment/ 0 1 ^{: Counter increment/decrement mode}
Decrement Control Bit
1 0 : Two-phase pulse signal processing
mode⁽³⁾
RW
1 1 : Do not set to this value
Nothing is assigned. When write, set to "0".
(b7)
When read, its content is indeterminate.
NOTES:
1. The base timer is reset after two fBT1 clock cycles when the base timer value matches the G1PO0
register setting. (See Figure 22.7 for details on the G1PO0 register.) When the RST1 bit is set to "1",
the G1POj register (j=1 to 7) for the waveform generating function and communication function must
be set to a value smaller than the G1PO0 register.
2. The IPSA_0 bit in the IPSA register can select the INT0 or INT1 pin.
3. In two-phase pulse signal processing mode, the base timer is not reset, even though the RST1 bit is
set to "1", if the counter is decremented after two clock cycles when the base timer value matches the
G1PO0 register setting.
Figure 22.4 G1BCR1 Register
Rev. 1.00 Sep. 08, 2005 ^{Page 266} of 479
REJ09B0204-0100