UPD48576209F1 Datasheet, PDF (28/54 Pages) Renesas Technology Corp – 576M-BIT Low Latency DRAM

µPD48576209F1, µPD48576218F1, µPD48576236F1
Figure 2-14. READ Burst Basic Sequence: BL=2, RL=4, Configuration 1
0
1
2
3
4
5
6
7
8
CK#
CK
COMMAND
RD
RD
RD
RD
RD
RD
RD
RD
RD
ADDRESS
A
BA0
A
BA1
A
BA2
A
BA3
A
BA0
A
BA7
A
BA6
A
BA5
A
BA4
RL = 4
QKx
QKx#
QVLD
DQ
Q0a Q0b Q1a Q1b Q2a Q2b Q3a Q3b Q0a
Don't care
Undefined
Figure 2-15. READ Burst Basic Sequence: BL=4, RL=4, Configuration 1
0
1
2
3
4
5
6
7
8
CK#
CK
COMMAND
RD
NOP
RD
NOP
RD
NOP
RD
NOP
RD
ADDRESS
A
BA0
A
BA1
A
BA0
A
BA1
A
BA3
RL = 4
QKx
QKx#
QVLD
DQ
Q0a Q0b Q0c Q0d Q1a Q1b Q1c Q1d Q0a
Don't care
Undefined
Remark RD : READ command
A/BAp : Address A of bank p
RL : READ latency
Qpq : Data q from bank p
R10DS0256EJ0101 Rev. 1.01
Jan. 15, 2016
Page 28 of 53