H8-3577 Datasheet, PDF (279/733 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcomputer

Section 11 16-Bit Free-Running Timer
Bit 1—Timer Overflow Flag (OVF): This status flag indicates that the FRC has overflowed
(changed from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware,
however, and cannot be set by software.
Bit 1
OVF
0
1
Description
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
[Setting condition]
When FRC changes from H'FFFF to H'0000
(Initial value)
Bit 0—Counter Clear A (CCLRA): This bit selects whether the FRC is to be cleared at compare-
match A (when the FRC and OCRA values match).
Bit 0
CCLRA
0
1
Description
FRC clearing is disabled
FRC is cleared at compare-match A
(Initial value)
11.2.8 Timer Control Register (TCR)
Bit
Initial value
Read/Write
7
IEDGA
0
R/W
6
IEDGB
0
R/W
5
IEDGC
0
R/W
4
IEDGD
0
R/W
3
BUFEA
0
R/W
2
BUFEB
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture
signals, enables the input capture buffer mode, and selects the FRC clock source.
TCR is initialized to H'00 by a reset and in hardware standby mode
Bit 7—Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A
signal (FTIA).
Rev. 3.00 Mar 17, 2006 page 255 of 706
REJ09B0303-0300