H8-3577 Datasheet, PDF (131/733 Pages) Renesas Technology Corp – 8-Bit Single-Chip Microcomputer

Section 7 Universal Serial Bus Interface (USB)
Name
Abbreviation R/W
Initial Value Address
Serial timer control register
STCR
R/W
H'00
H'FFC3
Module stop control register
MSTPCRH R/W
H'3F
H'FF86
MSTPCRL R/W
H'FF
H'FF87
Notes: 1. Write-only or read-only depending on the transfer direction set in the endpoint direction
register.
2. Only 1 can be written.
3. Only 0 can be written after reading 1 to clear the flags.
7.2 Register Descriptions
In the USB protocol, the host transmits a token to initiate a single data transfer (a transaction). A
transaction consists of a token packet, data packet, and handshake packet. The token packet
contains the address endpoint of the transfer target device and the transfer type, the data packet
contains data, and the handshake packet contains information relating to transfer setup/non-setup.
In data transfer from the host to a slave, the host transmits an OUT token or SETUP token,
followed by data (an OUT or SETUP transaction). In data transfer from a slave to the host, the
host transmits an IN token and waits for data from the slave (an IN transaction). In the following
descriptions, these host-based IN and OUT operations may be referred to as “input” and “output.”
Also, items relating to host input transfer may be designated “IN” (IN transaction, IN-FIFO,
EP0in, etc.), while items relating to host output transfer are designated “OUT” (OUT transaction,
OUT-FIFO, EP0out, etc.).
Where an explicit expression such as “transmitted by the host” or “received by the host” is not
used, the terms “transmission” and “reception” refer to transmission and reception from the
standpoint of the USB module and slave CPU.
7.2.1 USB Data FIFO
The FIFO, together with EPDR, functions as an intermediary role in data transfer between the H8
CPU (slave) and the USB function. The USB function uses the FIFO to execute data transfer to
and from the USB host (host).
The H8/3567U and H8/3564U have an on-chip 64-byte FIFO. This FIFO is divided into four 16-
byte FIFOs, used for endpoint 0 host input transfer and host output transfer (control transfer),
endpoint 1 host input transfer (interrupt transfer), and endpoint 2 host input transfer or host output
transfer. If endpoint 2 is not used, a 32-byte length can be selected for the endpoint 1 FIFO. The
maximum data packet size is set at half the number of FIFO bytes.
Rev. 3.00 Mar 17, 2006 page 107 of 706
REJ09B0303-0300