UPD48288118AF1 Datasheet, PDF (27/52 Pages) Renesas Technology Corp – 288M-BIT Low Latency DRAM

µPD48288118AF1
Figure 2-16. READ followed by WRITE, BL=2, RL=4, WL=5, Configuration 1
0
1
2
3
4
5
6
7
CK#
CK
COMMAND
RD
WR
WR
NOP
NOP
NOP
NOP
NOP
ADDRESS
A
BA0
A
BA1
A
BA2
RL = 4
DK#
DK
D
WL = 5
D1a D1b D2a D2b
Q
QKx
QKx#
Q0a Q0b
Don't care
Undefined
Figure 2-17. READ followed by WRITE, BL=4, RL=4, WL=5, Configuration 1
0
1
2
3
4
5
6
7
CK#
CK
COMMAND RD
WR
RD
NOP
NOP
NOP
NOP
NOP
ADDRESS
A
BA0
A
BA1
A
BA2
DK#
DK
D
Q
QKx
QKx#
RL = 4
WL = 5
D1a D1b D1c D1d
Q0a Q0b Q0c Q0d Q2a Q2b Q2c
Don't care
Undefined
Remark
WR : WRITE command
RD : READ command
A/BAp : Address A of bank p
WL : WRITE latency
RL : READ latency
Dpq : Data q to bank p
Qpq : Data q from bank p
R10DS0255EJ0101 Rev. 1.01
Jan. 15, 2016
Page 27 of 51