UPD48288118AF1 Datasheet, PDF (26/52 Pages) Renesas Technology Corp – 288M-BIT Low Latency DRAM

µPD48288118AF1
Figure 2-14. READ Burst Basic Sequence: BL=2, RL=4, Configuration 1
0
1
2
3
4
5
6
7
8
CK#
CK
COMMAND
RD
RD
RD
RD
RD
RD
RD
RD
RD
ADDRESS
A
BA0
QKx
QKx#
QVLD
Q
A
A
BA1
BA2
RL = 4
A
BA3
A
A
A
A
A
BA0
BA7
BA6
BA5
BA4
Q0a Q0b Q1a Q1b Q2a Q2b Q3a Q3b Q0a
Don't care
Undefined
Figure 2-15. READ Burst Basic Sequence: BL=4, RL=4, Configuration 1
0
1
2
3
4
5
6
7
8
CK#
CK
COMMAND RD
NOP
RD
NOP
RD
NOP
RD
NOP
RD
ADDRESS
A
BA0
A
BA1
A
BA0
A
BA1
A
BA3
RL = 4
QKx
QKx#
QVLD
Q
Q0a Q0b Q0c Q0d Q1a Q1b Q1c Q1d Q0a
Don't care
Undefined
Remark RD
A/BAp
RL
Qpq
: READ command
: Address A of bank p
: READ latency
: Data q from bank p
R10DS0255EJ0101 Rev. 1.01
Jan. 15, 2016
Page 26 of 51