RMQCHA3636DGBA_15 Datasheet, PDF (25/30 Pages) Renesas Technology Corp – 36-Mbit DDR™ II+ SRAM 2-word Burst Architecture (2.0 Cycle Read latency)

RMQCHA3636DGBA, RMQCHA3618DGBA
TAP Controller Instruction Set
Preliminary Datasheet
IR2 IR1 IR0 Instruction
Description
Notes
The EXTEST instruction allows circuitry external to the component
package to be tested. Boundary scan register cells at output balls
are used to apply test vectors, while those at input balls capture test
00 0
EXTEST
results. Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary scan register
1,2,3,4
using the PRELOAD instruction. Thus, during the Update-IR state
of EXTEST, the output driver is turned on and the PRELOAD data is
driven onto the output balls.
The IDCODE instruction causes the ID ROM to be loaded into the
ID register when the controller is in capture-DR mode and places
0
0
1
IDCODE
the ID register between the TDI and TDO balls in shift-DR mode.
The IDCODE instruction is the default instruction loaded in at power
up and any time the controller is placed in the Test-Logic-Reset
state.
If the SAMPLE-Z instruction is loaded in the instruction register, all
RAM outputs are forced to an inactive drive state (high-Z), moving
01
0
SAMPLE-Z
the TAP controller into the capture-DR state loads the data in the
RAMs input into the boundary scan register, and the boundary scan
3,4
register is connected between TDI and TDO when the TAP
controller is moved to the shift-DR state.
0
1
1
RESERVED
The RESERVED instruction is not implemented but is reserved for
future use. Do not use this instruction.
When the SAMPLE instruction is loaded in the instruction register,
moving the TAP controller into the capture-DR state loads the data
in the RAMs input and I/O buffers into the boundary scan register.
Because the RAM clock(s) are independent from the TAP clock
1
0
0
SAMPLE (TCK) it is possible for the TAP to attempt to capture the I/O ring
(/PRELOAD) contents while the input buffers are in transition (i.e., in a metastable
3,4
state). Although allowing the TAP to SAMPLE metastable input will
not harm the device, repeatable results cannot be expected.
Moving the controller to shift-DR state then places the boundary
scan register between the TDI and TDO balls.
1
0
1
RESERVED
The RESERVED instruction is not implemented but is reserved for
future use. Do not use this instruction.
1
1
0
RESERVED
The RESERVED instruction is not implemented but is reserved for
future use. Do not use this instruction.
The BYPASS instruction is loaded in the instruction register when
the bypass register is placed between TDI and TDO. This occurs
1
1
1
BYPASS when the TAP controller is moved to the shift-DR state. This allows
the board level scan path to be shortened to facilitate testing of
other devices in the scan path.
Notes:
1.
2.
3.
4.
Data in output register is not guaranteed if EXTEST instruction is loaded.
After performing EXTEST, power-up conditions are required in order to return part to normal operation.
RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus
hold time (t_CS plus t_CH). The RAMs clock inputs need not be paused for any other TAP operation except
capturing the I/O ring contents into the boundary scan register.
Clock recovery initialization cycles are required after boundary scan.
R10DS0240EJ0002 Rev.0.02
Dec. 01, 2014
Page 25 of 29