RMQCHA3636DGBA_15 Datasheet, PDF (15/30 Pages) Renesas Technology Corp – 36-Mbit DDR™ II+ SRAM 2-word Burst Architecture (2.0 Cycle Read latency)

RMQCHA3636DGBA, RMQCHA3618DGBA
DC Characteristics
Preliminary Datasheet
(T_A = -40 to +85°C, V_DD = 1.8V ± 0.1V, V_DDQ = 1.5V, V_REF = 0.75V)
Parameter
Symbol Test condition
MIN.
MAX.
Unit Notes
450MHz
400MHz
Operating Supply
IDD
Current
(x36)
(x18)
770
710
mA
600
550
1,2,3
(Write / Read)
Standby Supply
ISB1
Current
(x36)
(x18)
370
350
mA
320
310
2,4,5
(NOP)
Input leakage current
Output leakage current
Output high voltage
ILI
ILO
VOH
(Low)
|IOH| ≤ 0.1 mA
-2
-5
VDDQ − 0.2
2
5
VDDQ
μA 9
μA 10
V
8
Output low voltage
VOH
VOL
(Low)
Note 6
IOL ≤ 0.1 mA
VDDQ/2 − 0.12
VSS
VDDQ/2 + 0.12
0.2
V8
V
8
VOL
Note 7
VDDQ/2− 0.12
VDDQ/2+ 0.12
V8
Notes:
1. All inputs (except ZQ, V_REF) are held at either V_IH or V_IL.
2. I_OUT = 0 mA. V_DD = V_DD max, t_KHKH = t_KHKH min.
3. Operating supply currents (I_DD) are measured at 100% bus utilization. I_DD of DDR family is current of
device with 100% write cycle (if I_DD(Write) > I_DD(Read)) or 100% read cycle (if I_DD(Write) <
I_DD(Read)).
4. All address / data inputs are static at either V_IN > V_IH or V_IN < V_IL.
5. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ and
WRITE cycles are completed. )
6. Outputs are impedance-controlled. |I_OH| = (V_DDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
7. Outputs are impedance-controlled. I_OL = (V_DDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
8. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
9. 0 ≤ V_IN ≤ V_DDQ for all input balls (except V_REF, ZQ, TCK, TMS, TDI ball).
10. 0 ≤ V_OUT ≤ V_DDQ (except TDO ball), output disabled.
R10DS0240EJ0002 Rev.0.02
Dec. 01, 2014
Page 15 of 29