M5M5Y5636TG-25 Datasheet, PDF (25/30 Pages) Mitsubishi Electric Semiconductor – 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

JTAG TAP CONTROLLER STATE DIAGRAM
MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
Test-Logic-Reset
1
0
Run-Test/Idle ¹
0
Select-DR-Scan ¹
0
1 _Capture-DR
0
Shift-DR
1
0
1
Exit1-DR
0
Pause-DR
1
0
Exit2-DR
0
1
Update-DR
1
0
1
Select-IR-Scan
0
1 _Capture-IR
0
Shift-IR
1
0
1
Exit1-IR
0
Pause-IR
1
0
Exit2-IR
0
1
Update-IR
1
0
TAP CONTROLLER DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=1.70~1.95V, unless otherwise noted)
Symbol
Parameter
Condition
Limits
Unit
Min
Max
VIHT
Test Port Input High Voltage
0.65*VDDQ VDDQ+0.3 ** V
VILT
Test Port Input Low Voltage
-0.3 **
0.35*VDDQ V
VOHT Test Port Output High Voltage
IOH=-100µA
VDDQ-0.1
-
V
VOLT Test Port Output Low Voltage
IOL=+100µA
-
0.1
V
IINT
TMS, TCK and TDI Input Leakage Current
-10
10
µA
IOLT
TDO Output Leakage Current
Output Disable, VOUT=0V~VDDQ
-10
10
µA
Note37. **Input Undershoot/Overshoot voltage must be –1.0V<Vi<VDDQ+1V(max. 3.6V) with a pulse width not to exceed 20% tTCK.
24/29
Preliminary
M5M5Y5636TG REV.0.6