UPD48576118F1 Datasheet, PDF (23/52 Pages) Renesas Technology Corp – 576M-BIT Low Latency DRAM

µPD48576118F1
Figure 2-10. WRITE Followed By READ: BL=2, RL=4, WL=5, Configuration 1
0
1
2
3
4
5
6
7
8
9
CK#
CK
COMMAND WR
RD
RD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS
A
BA0
A
BA1
A
BA2
WL = 5
RL = 4
DK#
DK
D
D0a D0b
Q
QKx
QKx#
Q1a Q1b Q2a Q2b
Don't care
Undefined
Figure 2-11. WRITE Followed By READ: BL=4, RL=4, WL=5, Configuration 1
0
1
2
3
4
5
6
7
8
9
CK#
CK
COMMAND WR
RD
WR
RD
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS
A
BA0
A
BA1
A
BA2
A
BA3
WL = 5
RL = 4
DK#
DK
D
D0a D0b D0c D0d D2a D2b D2c D2d
Q
QKx
QKx#
Remark
WR : WRITE command
RD : READ command
A/BAp : Address A of bank p
WL : WRITE latency
RL : READ latency
Dpq : Data q to bank p
Qpq : Data q from bank p
R10DS0257EJ0101 Rev. 1.01
Jan. 15, 2016
Q1a Q1b Q1c Q1d Q3a Q3b Q3c Q3d
Don't care
Undefined
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