SH7211_09 Datasheet, PDF (23/26 Pages) Renesas Technology Corp – MTU2 Three-Phase Complementary PWM Output Function

Register Name
Timer output master
enable register
(TOER)
Timer interrupt
enable register_3
(TIER_3)
Timer start register
(TSTR)
Address
H'FFFE420A
H'FFFE4208
H'FFFE4280
SH7211 Group
MTU2 Three-Phase Complementary
PWM Output Function (Complementary PWM Mode)
Value
H'FF
H'01
H'C0
Description
Specifies the output settings for the MTU2 output
pins.
• OE4D = B'1: Enable MTU2 output on
TIOC4D pin.
• OE4C = B'1: Enable MTU2 output on
TIOC4C pin.
• OE3D = B'1: Enable MTU2 output on
TIOC3D pin.
• OE4B = B'1: Enable MTU2 output on TIOC4B
pin.
• OE4A = B'1: Enable MTU2 output on TIOC4A
pin.
• OE3B = B'1: Enable MTU2 output on TIOC3B
pin.
Enables or disables interrupt requests.
• TGIEA= B'1: Enable interrupt requests
(TGIA) by TGFA bit.
Starts or stops TCNT operation for channels 0 to
4.
• CST4 = B'1: Start TCNT_4 count operation.
• CST3 = B'1: Start TCNT_3 count operation.
Stop count operation by TCNT_2, TCNT_1, and
TCNT_0. Make counter operation bit settings for
TCNT_4 and TCNT_3 at the same time.
2.5.4 Interrupt Controller (INTC)
Table 9 gives a list of settings for registers of the interrupt controller (INTC).
Table 9 Interrupt Controller (INTC)
Register Name
Interrupt priority level
setting register 10
(IPR10)
Address
H'FFFE0C08
Setting
H'00F0
Description
Sets interrupt priority levels (level 0 to 15).
• Bits 15 to 12 = B'0000: MTU2 (TGI2A and
TGI2B) interrupt level = 0
• Bits 11 to 8 = B'0000: MTU2 (TCI2V and
TCI2U) interrupt level = 0
• Bits 7 to 4 = B'1111: MTU3 (TGI3A to TGI3D)
interrupt level = 15
• Bits 3 to 0 = B'0000: MTU3 (TCI3V) interrupt
level = 0
The TGI3A interrupt is used by the reference
program.
REJ06B0891-0100/Rev.1.00
July 2009
Page 23 of 26