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R1QGA7236ABG_15 Datasheet, PDF (22/39 Pages) Renesas Technology Corp – 72-Mbit QDR™II+ SRAM 4-word Burst
Common
R1QGA72 / R1QKA72 Series
Output load conditions Output load and voltage conditions
1.8V±0.1V 1.5V
VDDQ / 2
= 0.75V
VDD
VDDQ
VREF
SRAM
VSS
Q
250Ω
ZQ
Z0 = 50Ω
VDDQ / 2
= 0.75V
50Ω
AC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit Notes
Input high voltage
Input low voltage
Notes:
VIH (AC)
VREF + 0.2
⎯
⎯
V 1, 2, 3, 4
VIL (AC)
⎯
⎯
VREF – 0.2
V
1, 2, 3, 4
1. All voltages referenced to VSS (GND).
During normal operation, VDDQ must not exceed VDD.
2. These conditions are for AC functions only, not for AC parameter test.
3. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2
Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates
less than tKHKH (min).
4. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level,
VIL (AC) or VIH (AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level,
VIL (DC) or VIH (DC).
Rev. 0.11 : 2013.01.15
R10DS0183EJ0011
PAGE:22