R1QGA7236ABG_15 Datasheet, PDF (12/39 Pages) Renesas Technology Corp – 72-Mbit QDR™II+ SRAM 4-word Burst

IIP
R1QGA72 / R1QKA72 Series
Thevenin termination
Other LSI
Output
Buffer
SRAM with ODT
V_DDQ
2 × R_THEV
ZQ
2 × R_THEV
Input
Buffer
RQ
V_SS
V_SS
ODT pin (R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series)
ODT On/Off timing
Notes
Pin name
Option 1
Option 2
ODT pin = High
ODT pin = Low
or Floating
3
D₀ ~ D_n in separate I/O devices
DQ₀ ~ DQ_n
in common I/O devices
Always On
Off: First Read Command
+ Read Latency
- 0.5 cycle
On: Last Read Command
+ Read Latency
+ BL/2 cycle + 0.5 cycle
(See below timing chart)
Always Off
1
Always Off
2
/BW_x
K, /K
Always On
Always On
Always Off
Always Off
Notes:
1. Separate I/O devices are R1QD, R1QK, R1QP series.
2. Common I/O devices are R1QE, R1QF, R1QL, R1QM series.
3. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with
option 2, please contact Renesas sales office.
Rev. 0.11 : 2013.01.15
R10DS0183EJ0011
PAGE:12