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| H838024 Datasheet, PDF (215/697 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer Super Low Power Series | |||
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Section 6 ROM
Increment address
Erase start
SWE bit â 1
Wait 1 µs
nâ1
Set EBR
Enable WDT
ESU bit â 1
Wait 100 µs
E bit â 1
Wait 10 ms
E bit â 0
Wait 10 µs
ESU bit â 0
Wait 10 µs
Disable WDT
EV bit â 1
Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 µs
Read verify data
No
Verify data = all 1s ?
Yes
No
Last address of block ?
Yes
EV bit â 0
Wait 4 µs
nân+1
EV bit â 0
Wait 4µs
No
All erase block erased ?
Yes
SWE bit â 0
Wait 100 µs
n â¤100 ?
Yes
No
SWE bit â 0
Wait 100 µs
End of erasing
Erase failure
Figure 6.11 Erase/Erase-Verify Flowchart
Rev. 7.00 Mar 10, 2005 page 173 of 652
REJ09B0042-0700
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