H8S2615 Datasheet, PDF (214/479 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

8.7.2 Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 8.38 shows the timing for setting
of the TGF flag in TSR on compare match, and TGI interrupt request signal timing.
φ
TCNT input
clock
TCNT
N
N+1
TGR
N
Compare
match signal
TGF flag
TGI interrupt
Figure 8.38 TGI Interrupt Timing (Compare Match)
TGF Flag Setting Timing in Case of Input Capture: Figure 8.39 shows the timing for setting of
the TGF flag in TSR on input capture, and TGI interrupt request signal timing.
φ
Input capture
signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 8.39 TGI Interrupt Timing (Input Capture)
Rev. 2.00, 05/04, page 180 of 442