M66288FP Datasheet, PDF (21/24 Pages) Renesas Technology Corp – 262144-word x 8-bit x 3-FIFO MEMORY

M66288FP
N-bit Delay 2
(Sliding timings of WRES and RRES at a cycle corresponding to delay length)
Reset cycle 0 cycle
1 cycle
2 cycle
WCK
RCK
tRESS tRESH
WRES
RRES
tDS tDH
n-1 cycle n cycle
Reset cycle 0 cycle
n+1 cycle
1 cycle
n+2 cycle
2 cycle
n+3 cycle ·····Write side
3 cycle
·····Read side
tRESS tRESH
tDS tDH
Dn
(0)
(1)
(2)
(n-2)
(n-1)
(n)
(n+1)
(n+2)
(n+3)
Delay length n
tAC
tOH
Qn
(0)
(1)
(2)
(3)
262144 ≥ n ≥ 16
WE, RE = "L"
N-bit Delay 3
(Sliding address by disabling RE at a cycle corresponding to delay length)
Reset cycle 0 cycle
1 cycle
2 cycle
n-1 cycle
n cycle
0 cycle
n+1 cycle
1 cycle
n+2 cycle
2 cycle
n+3 cycle ·····Write side
3 cycle
·····Read side
WCK
RCK
WRES
RRES
tRESS tRESH
tNREH tRES
RE
tDS tDH
tDS tDH
Dn
(0)
(1)
(2)
(n-2)
(n-1)
(n)
(n+1)
(n+2)
(n+3)
Delay length n
tAC
tOH
HIGH-Z
Qn
(0)
(1)
(2)
(3)
262144 ≥ n ≥ 16
WE = "L"
REJ03F0156-0310 Rev.3.10 Apr.04.2008
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